1. Field of the Invention
The present invention relates to a semiconductor wafer direct bonding technique and, more particularly, to a pair of semiconductor wafers bonded to each other to have a dielectrically isolated structure, and a method of manufacturing the same.
2. Description of the Related Art
A technique for directly bonding a pair of semiconductor substrates such as silicon wafers to each other at a clean, mirror-polished surfaces thereof to provide an integrated wafer has been developed. This technique is well known as "Silicon-to-Silicon direct bonding technique". When this direct bonding technique is used, various types of semiconductor wafers can be fabricated. For example, when a silicon wafer having a resistivity of 1/1,000 .OMEGA..cm and a silicon wafer having a resistivity of several hundreds .OMEGA..cm are directly bonded to each other, a silicon wafer having a laminated structure of low- and high-resistivity semiconductor layers can be easily obtained. When one or both of these wafers to be bonded to each other are subjected to surface-oxidation, a wafer having a dielectrically isolated silicon laminated structure can be obtained.
When a dielectrically isolated silicon substrate is fabricated using the direct bonding technique, the following advantages can be obtained as compared with other isolation technologies such as p-n junction isolation, conventional dielectric isolation using a thick polysilicon body, and an SIMOX method wherein oxygen ions are implanted to inside the silicon bulk to form an oxide film therein. That is, (1) the quality of the silicon layer serving as an active layer can be kept to be excellent, (2) the thickness of the silicon layer can be artibrarily set, and (3) manufacturing processes can be relatively easily performed. Because of the above reasons, the above-mentioned "Silicon-to-Silicon direct bonding technique" is widely utilized for formation of a dielectrically isolated and directly bonded pair of silicon substrates having different characteristics.
The dielectrically isolated substrate fabricated by the direct bonding method, however, has the following problems. The first problem is a warp of bonded substrates. Two silicon substrates are directly bonded during a thermal treatment. When a substrate temperature returns to room temperature, a stress is generated between the silicon substrates and a silicon oxide film sandwiched therebetween due to a difference in thermal shrinkage. Since the thermal expansion coefficient of the silicon substrates is larger than that of the silicon oxide film, a shrinkage of the silicon substrates due to decrease in temperature is more considerable. As a result, at room temperature, a tensile stress is generated in the silicon substrates, while a compressive stress is generated in the silicon oxide film. In general, one silicon substrate on which circuit elements such as transistors are formed is polished so as to be thinner than the other silicon substrate serving as a support base layer. These facts result in warpage of the substrate structure. Such a warp in the directly bonded silicon substrates prevents effective execution of the following wafer manufacturing process such as a PEP process. In particular, as an increase in diameter of the wafer and miniaturization of circuit elements progress, the above problems become more serious.
The second problem is that it is difficult to achieve bonding of peripheral portions of the directly bonded semiconductor wafers without failure. Initially manufactured silicon wafers have poor parallel geometry in their peripheral portions. If two silicon substrates with such poor parallel geometry are bonded directly, incomplete bonding occurs in their peripheral portions, and their mechanical strength is decreased (particularly in the peripheral portion of a thinner wafer). The decrease in mechanical strength causes a problem that the wafer may be broken in the following circuit element formation steps.
In order to solve the above problems, it is necessary to remove a predetermined area of the incompletely bonded peripheral wafer portions, and to use only completely bonded central wafer portion. However, when the peripheral wafer portion is removed, an orientation flat formed therein is also removed. If no orientation flat is provided, accurate fabrication of element isolation V-shaped groove and integrated circuit patterns onto the wafer in the following steps cannot be performed.